What is Co Packaged Optics CPO? The Guide to Next-Gen AI Data Center Interconnects
Jul 11, 2026
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TL;DR: Co packaged optics (CPO) is an advanced heterogeneous integration technology that packages optical engines (transceivers) and electrical switch chips (ASICs) together on a single common substrate, replacing traditional copper board traces with direct, millimeter-scale high-density optical connections. By placing the optical transceivers-often referred to as photonic chiplets-directly inside the switch package rather than as separate modules on the front panel, CPO reduces the electrical signal path from centimeters to millimeters. This revolutionary architecture drastically lowers power consumption by up to 70%, increases bandwidth density, and eliminates the physical limits of copper cabling in next-generation AI clusters and hyperscale data centers. If you are wondering what is co packaged optics and why it is the key to scaling future network infrastructure, this comprehensive technical guide breaks down its inner workings, packaging structures, power efficiency, and key industry players.
High-speed networks have hit a physical wall that traditional copper cabling cannot climb. As artificial intelligence (AI) clusters scale up, copper wires struggle to handle massive data rates without burning through power and generating extreme heat.
How do we keep data flowing at 800G, 1.6T, and beyond without melting our switches?
The answer lies in a groundbreaking architectural shift: co packaged optics (CPO). But what is co packaged optics , and why is it suddenly the most talked-about technology in the optical communication industry?
At COBTEL, with over 20 years in the optical communication and network cabling industry, we have watched fiber transceiver types evolve from 1G SFP modules to today's 1.6T configurations. CPO is the next leap, and understanding it is critical for anyone designing networks for AI, cloud, or high-performance computing.
What Is Co Packaged Optics (CPO)?
Co packaged optics (CPO) is an advanced heterogeneous integration technology that packages optical engines (transceivers) and electrical switch chips (ASICs) together on a single substrate, replacing long copper board traces with direct, millimeter-scale high-density optical connections.
At its fundamental level, co packaged optics (CPO) represents a transition from a modular transceiver system to a highly integrated co packaged chip system. To understand CPO, think of a traditional optical transceiver as an 'office translator.' In a standard setup, this translator sits at the very edge of the switch (the front panel). When the main switch chip (the speaker) wants to send data, it has to shout across a long, noisy PCB copper trace, through connectors, all the way to the front panel. The translator at the front panel then translates those electrical signals into light and sends them down the fiber.
CPO moves the translator directly into the same office as the speaker. By taking the optical engine (the part that converts electricity to light) out of the separate front-panel box and placing it directly onto the same multi-chip substrate as the main switch ASIC, the travel distance of electrical signals shrinks from several centimeters to just 2 to 5 millimeters. Because this distance is so short, the power required to push high-frequency signals drops dramatically, virtually eliminating signal degradation and transmission errors.
Using another everyday analogy: traditional optical modules are like placing your shipping distribution center in a neighboring city. Every time you want to deliver a package, you have to drive a truck on a long highway. CPO is like moving the distribution center directly next door to your factory warehouse. The travel distance shrinks from several centimeters to just a few millimeters.
Because the travel distance is so short, you do not need as much power to push the signal, which drastically reduces power loss and transmission errors.
Here is a quick comparison showing how CPO shifts the paradigm:
Feature
Traditional Pluggable Module
Co Packaged Optics (CPO)
Optical Engine Placement
Front panel of the switch
Inside the switch, on the chip substrate
Electrical Path Length
10 to 30 centimeters
2 to 5 millimeters
Power Consumption
High (due to long copper paths)
Low (up to 70% power savings)
DSP Dependency
High (requires heavy signal tuning)
Low (can often eliminate the DSP entirely)
Maintenance & Swap
Easy (hot-swappable from the front)
Complex (requires specialized modular design)
Understanding what is an optical module at its fundamental level is the starting point for understanding CPO. While traditional modules are independent, pluggable, external boxes, CPO represents a transition from a "modular system" to a "co packaged chip system."
Why Do Traditional Pluggable Modules Hit Their Physical Limits?
Traditional pluggable modules hit their physical limits at single-channel rates of 224Gbps because high-frequency electrical signals degrade rapidly over copper board traces, requiring power-hungry digital signal processors (DSPs) to restore signal integrity. For the last 20 years, pluggable transceivers have been the bedrock of data communications. If a module broke, an engineer could pull it out and slide in a new one without shutting down the entire switch. This plug-and-play simplicity made scaling data centers incredibly easy.
However, as single-channel speeds push toward 224Gbps, high-frequency electrical signals suffer from extreme attenuation (loss of signal strength) when they travel through copper tracks on a printed circuit board (PCB). At these rates, the signal deteriorates so fast that it arrives looking like a fuzzy mess of noise. To clean it up, traditional transceivers rely on a Digital Signal Processor (DSP) chip, which acts as a high-speed reconstructor. However, a single DSP chip inside an optical module can consume between 5 to 10 watts of power, leading to extreme thermal bottlenecks when multiplied across dozens of transceivers. CPO solves this by removing the copper path almost entirely.
How Does CPO Save So Much Power?
The extreme power-saving benefits of CPO come from two main areas:
Eliminating or Downsizing the DSP: Because the distance between the switch chip (ASIC) and the CPO optical engine is only a few millimeters, the electrical signal remains crisp and clean. The system no longer needs a heavy, power-hungry DSP to perform complex signal restoration, instantly cutting 5 to 10 watts of power per port.
Reducing Driver Power:When signal lines are short, electrical amplifiers (drivers) do not need to push nearly as much voltage to cross the gap. This drops the driver power down to a fraction of what traditional systems require.
Per-Port Savings: According to data released by NVIDIA, switching to a CPO-enabled design reduces individual port power consumption from 30 watts down to just 9 watts (a 70% decrease).
System-Wide Savings: In scale-up AI architectures, Meta's hardware analysis showed that an 800G traditional pluggable module consumes roughly 15W, whereas the optical engine inside Broadcom's Bailly CPO switch consumes only 5.4W per 800G of bandwidth delivered (a 65% power saving). This elimination of heat at the chip level makes green, highly sustainable AI computing a reality.
What Does a CPO System Look Like Inside?
A standard CPO system consists of three core components: a silicon photonics engine for electro-optical conversion, a high-precision fiber optic array (FAU) for external connectivity, and an application-specific integrated circuit (ASIC) switch chip acting as the brain.
Inside a co packaged optics design, the physical layout changes from a spread-out board to a highly dense, integrated micro-system. Here are the three pillars that make up its interior:
The Silicon Photonics Engine (PIC): Relies on Silicon Photonics (SiPh). Photonic Integrated Circuits (PICs) are manufactured using standard CMOS processes, allowing microscopic optical waveguides, modulators, and detectors to be printed directly onto a silicon chip.
High-Precision Fiber Array Unit (FAU): Once the PIC converts electrical signals to light, the FAU aligns dozens of individual fibers to the optical ports on the PIC with microscopic precision (micron-level end-face tolerances).
The Switch ASIC (Core Brain): The central processor managing network routing, placed directly next to the PIC on a single multi-chip package substrate using 2.5D or 3D stacking.
The External Laser Source (ELS): Putting the Bulb Outside the Oven
There is one major design challenge inside a CPO package: heat. The silicon switch ASIC gets incredibly hot (running like a small oven), but lasers are highly sensitive to temperature. If a laser chip gets too hot, its efficiency drops and its lifespan plummets.
To solve this, CPO architectures use an External Laser Source (ELS). The laser emitter is moved completely out of the hot chip package and placed onto the cool front panel of the switch. High-density fiber optic cables then guide the unmodulated laser light from the front panel into the CPO engine on the chip.
This design keeps the "heat-sensitive lightbulbs" safe from the "furnace," making the system much more reliable. To master these component dynamics, it is highly useful to study the main parts of an optical transceiver.
Main Packaging Structure Types of CPO Optical Modules
The way engineers physically arrange, connect, and stack the optical and electrical chips defines the CPO packaging structure. Today, the industry has settled on three primary structures: 2D, 2.5D, and 3D packaging.
1. 2D Packaging (Side-by-Side Integration)
In a 2D configuration, the Electronic Integrated Circuit (EIC) and the Photonic Integrated Circuit (PIC) are placed side-by-side on the same organic substrate or PCB.
Wire Bonding CPO: The EIC and PIC connect to the substrate, and thin gold wires bridge the gap between them. While this is highly flexible and simple to build, the wire loops create high parasitic capacitance, which limits high-speed performance.
Flip-Chip CPO: The chips are flipped upside down, and small metal bumps connect them to a ceramic substrate. This provides a shorter signal path and better thermals, but multi-layer ceramic substrates are expensive.
Fan-Out Wafer-Level Packaging (FOWLP): The PIC and EIC are molded into a synthetic polymer layer, and high-density metal lines (Redistribution Layers, or RDLs) are printed over them to link them. This completely eliminates wire bonds and bumps, creating a very thin, high-performance module.
Real-World Example: Broadcom's Bailly 51.2T CPO switch uses FOWLP to package eight optical engines around the central switch ASIC.
2. 2.5D Packaging (Interposer-Based Integration)
2.5D packaging introduces an extra layer called an interposer between the active chips and the bottom substrate. The active chips sit on top of this interposer, which contains incredibly dense, microscopic wiring to route signals between them.
Silicon Interposer: The PIC and EIC sit on a thin layer of silicon. This matches the thermal expansion of the chips perfectly, preventing physical warping. However, silicon is a semiconductor, which can cause high-frequency signals to bleed energy into the substrate.
Glass Interposer: Chips sit on a glass interposer. Glass is an exceptional electrical insulator, which keeps high-frequency signals clear.
OFC 2026 Milestone: Intel demonstrated a glass-substrate CPO prototype at the 2026 Optical Fiber Communication Conference, demonstrating a 10x increase in interconnect density.
EMIB (Embedded Multi-die Interconnect Bridge): Instead of a giant, expensive interposer, a tiny, thin silicon "bridge" is embedded inside the organic substrate right under the chip edges to link them. This saves money and maintains excellent signal integrity.
3. 3D Packaging (Vertical Stacking)
3D packaging represents the ultimate evolution of CPO. Instead of placing the optical and electrical chips side-by-side, engineers stack them vertically, one directly on top of the other.
PIC as the Interposer: The electronic chip (EIC) is stacked directly on top of the optical chip (PIC) using advanced copper-to-copper hybrid bonding.
Platform Standard: TSMC's COUPE (Compact Universal Photonic Engine) 3D platform uses this approach, dropping parasitic capacitance by an incredible 85% and cutting signal latency by 95%.
EIC as the Interposer: The PIC is stacked on top of the EIC. This allows the hot electronic chip to connect directly to the bottom substrate for easier cooling.
Organic Substrate Embedding: Silicon photonics are embedded directly inside an organic substrate, using built-in polymer waveguides to route light. This is highly cost-effective but prone to warping under intense heat.
Here is a summary of the tradeoffs across these three structural approaches:
Packaging Type
Interconnect Density
Signal Integrity
Manufacturing Cost
Thermal Management
Commercial Readiness (as of 2026)
2D Packaging
Moderate
Moderate
Low to Moderate
Fair
Mature (Broadcom Bailly, Cisco SiliconOne)
2.5D Packaging
High
High
High
Good
Scaling up (CoWoS systems)
3D Packaging
Ultra-High
Excellent
Very High
Challenging (Requires liquid cooling)
Emerging (NVIDIA Quantum-X800, TSMC COUPE)
Who Is Building CPO? The Global Ecosystem Map
CPO is not a localized effort; it has sparked a massive global collaboration across silicon design, advanced packaging, laser manufacturing, and physical cabling infrastructure.
1. International Silicon and System Giants
NVIDIA: The most aggressive driver of CPO commercialization. NVIDIA's Quantum-X800 Q3450-LD liquid-cooled CPO switch (using TSMC's 3D COUPE platform) delivers 115.2 Tbps of total bandwidth across 144 ports, completely removing the DSP to save over 3 kilowatts of power per switch rack.
Broadcom: The early pioneer. Following its Bailly 51.2T CPO switch, Broadcom introduced the Tomahawk 6 Davisson CPO ASIC, achieving single-channel speeds of 200Gbps and cutting optical power consumption by 70%.
Intel: Capitalizing on over 20 years of research, Intel is focusing on Optical Compute Interconnects (OCI) to link CPU and GPU chips directly using high-bandwidth optical paths.
Cisco & Marvell: Building custom SiliconOne CPO routers and integrated 3D Silicon Photonics engines directly inside customized XPUs.
2. Semiconductor Foundries
TSMC: Providing the foundational manufacturing engine with its COUPE platform, enabling high-volume 3D hybrid bonding of optical and electrical circuits.
Precision Alignment (FAUs): Tianfu Telecom is a global leader in high-precision FAU manufacturing and 1.6T light engines, serving as a core supplier for high-end AI CPO systems.
Laser Emitters (ELS): Lumentum and Coherent are leading developers of external laser sources. Meanwhile, companies like Yuanjie Technology have built a strong market position supplying CW-DFB laser chips.
Switch and Cooling Infrastructure: Ruijie Networks, H3C, and cooling specialists like Envic provide CPO-ready liquid cooling setups to manage high heat loads.
4. COBTEL's Role in the Ecosystem
As an OEM manufacturer of advanced optical components, COBTEL plays a crucial role in the physical infrastructure layer. CPO systems utilize incredibly high fiber counts to route laser light and signals. Our high-precision MPO fiber patch cords and custom server cabinets are specifically engineered to support the sub-micron tolerances and high density required by CPO switches and AI accelerators.
Will CPO Completely Replace Traditional Pluggable Modules?
No, CPO and pluggable optical modules will co-exist for the foreseeable future, as pluggables remain ideal for long-distance, highly flexible, and hot-swappable links, while CPO targets short-reach, ultra-dense AI clusters. Pluggables remain the undisputed king of long-distance data center interconnects (DCI) where quick front-panel hot-swapping is essential. CPO is the ultimate master of short-distance, ultra-high bandwidth applications under 100 meters, such as GPU-to-GPU clusters in AI workloads where bandwidth density and power savings are the ultimate priorities. Near-Packaged Optics (NPO) serves as a bridging step, placing the optical engine on the motherboard next to the ASIC to significantly shorten the electrical path without the initial complexity of full 3D CPO packaging.
Pluggables: King of Long Distance and Flexibility
For long-distance data center interconnects (DCI)-such as linking two data centers across a city or state-traditional pluggable modules like our high-capacity 800G optical transceiver will remain the standard.
These links do not need ultra-dense chip integration, but they do require high flexibility. If a long-distance transmitter fails, swapping a front-panel pluggable module takes seconds and keeps the rest of the switch running.
CPO: Master of Short-Distance, Ultra-High Bandwidth
CPO's home is inside the AI cluster. For connecting GPUs to other GPUs, or linking spine switches inside a single hall where distances are short (under 100 meters), bandwidth density and power savings are the ultimate priorities.
In this space, CPO is unmatched.
Industry analysts estimate that CPO will account for roughly 1% of AI-related optical modules shipped. However, as 1.6T and 3.2T architectures scale up, CPO market penetration is projected to climb to 20%–35% between 2028 and 2030.
The Stepping Stone: Near-Packaged Optics (NPO)
Because the leap from traditional pluggables to full CPO is technically complex, the industry has embraced an intermediate step called Near-Packaged Optics (NPO).
Understanding what is an optical link module at its fundamental level is the starting point for understanding CPO. While traditional modules are independent, pluggable, external boxes, CPO represents a transition from a "modular system" to a "co packaged chip system."
Why Do Traditional Pluggable Modules Hit Their Physical Limits?
Traditional pluggable modules hit their physical limits at single-channel rates of 224Gbps because high-frequency electrical signals degrade rapidly over copper board traces, requiring power-hungry digital signal processors (DSPs) to restore signal integrity.
For the last 20 years, pluggable transceivers have been the bedrock of data communications. If a module broke, an engineer could pull it out and slide in a new one without shutting down the entire switch. This plug-and-play simplicity made scaling data centers incredibly easy.
However, as we push single-channel speeds toward 224Gbps, we run face-first into the laws of physics. High-frequency electrical signals suffer from extreme attenuation (loss of signal strength) when they travel through copper copper tracks on a printed circuit board (PCB).
At 224Gbps, the electrical signal deteriorates so fast that by the time it travels across 10 to 30 centimeters of copper board to reach the pluggable module, it is completely distorted. It arrives looking like a fuzzy mess of noise.
To solve this, traditional transceivers rely on a Digital Signal Processor (DSP) chip. The DSP acts like a high-speed reconstructor, using complex math to "guess" what the original signal looked like and clean it up.
But DSPs are incredibly power-hungry and expensive. A single DSP chip inside an optical module can consume between 5 to 10 watts of power. Multiply that by dozens of transceivers plugged into a single high-density switch, and you get a massive thermal problem. The switch faceplate turns into a virtual furnace.
Even our highly optimized 400G QSFP-DD transceivers push pluggable design to its absolute engineering limits. Beyond these speeds, trying to make copper traces work is no longer a matter of improving manufacturing; it is a physical bottleneck. CPO solves this not by trying to make copper better, but by removing the copper path almost entirely.
How Does CPO Save So Much Power?
CPO saves power by reducing the electrical path from several centimeters to a few millimeters, allowing systems to remove or scale down energy-intensive DSPs and lower laser driver requirements.
The power-saving benefits of CPO come from two main areas:
1. Eliminating or Downsizing the DSP
Because the distance between the switch chip (ASIC) and the CPO optical engine is only a few millimeters, the electrical signal has almost no room to degrade. It arrives crisp and clean.
This means the system does not need a heavy, power-hungry DSP to perform complex signal restoration. In many CPO designs, the DSP can be completely eliminated. This instantly cuts 5 to 10 watts of power consumption per port.
2. Reducing Driver Power
When signal lines are short, the electrical amplifiers (drivers) do not need to push nearly as much voltage to get the signal across. This drops the driver power down to a fraction of what traditional systems require.
The real-world energy savings of this shift are dramatic:
Per-Port Savings: According to data released by NVIDIA, switching to a CPO-enabled design reduces individual port power consumption from 30 watts down to just 9 watts (a 70% decrease).
System-Wide Savings: In scale-up AI architectures, Meta's hardware analysis showed that an 800G traditional pluggable module consumes roughly 15W, whereas the optical engine inside Broadcom's Bailly CPO switch consumes only 5.4W per 800G of bandwidth delivered (a 65% power saving).
Saving power does not just lower your electric bill; it also lowers cooling costs. In massive AI training clusters, cooling the hardware often takes almost as much power as running the processors themselves. By eliminating the heat at the chip level, CPO makes green, highly sustainable AI computing a reality.
What Does a CPO System Look Like Inside?
A standard CPO system consists of three core components: a silicon photonics engine for electro-optical conversion, a high-precision fiber optic array (FAU) for external connectivity, and an application-specific integrated circuit (ASIC) switch chip acting as the brain.
Inside a co packaged optics design, the physical layout changes from a spread-out board to a highly dense, integrated micro-system. Here are the three pillars that make up its interior:
1. The Silicon Photonics Engine (PIC)
Unlike traditional transceivers that use individual, separate lasers and optical components, CPO relies on Silicon Photonics (SiPh). Photonic Integrated Circuits (PICs) are manufactured using standard CMOS silicon processes (the same factories that make computer CPUs). This allows engineers to print microscopic optical waveguides, modulators, and detectors directly onto a silicon chip.
2. High-Precision Fiber Array Unit (FAU)
Once the silicon photonics engine converts electrical signals into light, that light must be funneled into glass fibers. The Fiber Array Unit (FAU) aligns dozens of individual fibers to the optical ports on the PIC with microscopic precision. Because the optical cores are only a few micrometers wide, even a tiny misalignment can ruin the connection.
When we manufacture high-density MPO and breakout fiber assemblies at COBTEL, micron-level end-face polishing is already a major engineering focus. In CPO systems, this precision is scaled directly onto the chip substrate.
3. The Switch ASIC (Core Brain)
This is the central processor that manages network routing. In CPO, this massive chip is placed directly next to the silicon photonics engine on a single multi-chip package substrate using advanced packaging technologies (like 2.5D or 3D stacking).
The External Laser Source (ELS): Putting the Bulb Outside the Oven
There is one major design challenge inside a CPO package: heat. The silicon switch ASIC gets incredibly hot (running like a small oven), but lasers are highly sensitive to temperature. If a laser chip gets too hot, its efficiency drops and its lifespan plummets.
To solve this, CPO architectures use an External Laser Source (ELS). The laser emitter is moved completely out of the hot chip package and placed onto the cool front panel of the switch. High-density fiber optic cables then guide the unmodulated laser light from the front panel into the CPO engine on the chip.
This design keeps the "heat-sensitive lightbulbs" safe from the "furnace," making the system much more reliable. To master these component dynamics, it is highly useful to study the main parts of an optical transceiver .
Main Packaging Structure Types of CPO Optical Modules
The way engineers physically arrange, connect, and stack the optical and electrical chips defines the CPO packaging structure. Today, the industry has settled on three primary structures: 2D, 2.5D, and 3D packaging.
1. 2D Packaging (Side-by-Side Integration)
In a 2D configuration, the Electronic Integrated Circuit (EIC) and the Photonic Integrated Circuit (PIC) are placed side-by-side on the same organic substrate or PCB.
Wire Bonding CPO: The EIC and PIC connect to the substrate, and thin gold wires bridge the gap between them. While this is highly flexible and simple to build, the wire loops create high parasitic capacitance, which limits high-speed performance.
Flip-Chip CPO: The chips are flipped upside down, and small metal bumps connect them to a ceramic substrate. This provides a shorter signal path and better thermals, but multi-layer ceramic substrates are expensive.
Fan-Out Wafer-Level Packaging (FOWLP):
Electronic chips (EIC) and optical chips (PIC) are embedded in an epoxy molding compound (EMC) substrate, with optoelectronic interconnection achieved through a redistribution layer (RDL). This completely eliminates wire bonds and bumps, creating a very thin, high-performance module. This design eliminates wire bonds or bumps, yielding a compact, high-performance, high-density package that shortens interconnect lines and optimizes signal integrity. The chip has a small footprint and is connected to the ASIC substrate via the fan-out region. However, the process is complex, involving wafer reconstitution, molding, and redistribution layer (RDL) formation, with each step affecting package reliability. Wafer reconstitution requires high positioning accuracy, and coefficient of thermal expansion (CTE) mismatch during molding can easily lead to wafer warpage and chip displacement.
A cross-section of hybrid optical packaging based on the FOWLP platform, suitable for (a) multimode and (b) single-mode applications. In multimode packaging, the direction of light propagation is vertical; in single-mode optical packaging, it is lateral.
Real-World Example: Broadcom's Bailly 51.2T CPO switch uses FOWLP to package eight optical engines around the central switch ASIC.
2. 2.5D Packaging (Interposer-Based Integration)
2.5D packaging introduces an extra layer called an interposer between the active chips and the bottom substrate. The active chips sit on top of this interposer, which contains incredibly dense, microscopic wiring to route signals between them.
Silicon Interposer:
PIC and EIC are flip-chip bonded onto a silicon interposer, which features a multi-layer RDL structure and may contain TSVs (Through-Silicon Vias) for connection to the PCB. Advantages include high integration density, a thin profile, integrated bumps, good CTE match with chip materials, reduced warpage, improved reliability, and high-bandwidth electrical interconnection. However, it faces high cost (due to TSV fabrication and insulation layer oxidation) and poor electrical performance (silicon is a semiconductor, leading to strong electromagnetic coupling with the substrate during signal transmission, which generates eddy currents and affects signal integrity).
Glass Interposer: Chips sit on a glass interposer. Glass is an exceptional electrical insulator, which keeps high-frequency signals clear.
OFC 2026 Milestone: Intel demonstrated a glass-substrate CPO prototype at the 2026 Optical Fiber Communication Conference, demonstrating a 10x increase in interconnect density .
Components such as PICs, drivers, and TIAs are flip-chip bonded onto a glass carrier substrate. Optical signals are transmitted through waveguides on the backside of the glass carrier substrate and coupled to optical fibers. Electrical signals are routed through metallized Through-Glass Vias (TGVs) in the glass carrier substrate. Glass has a higher Young's modulus and hardness, and its coefficient of thermal expansion can match that of silicon and PCB boards, reducing internal system stress, minimizing warpage in large chips, and improving yield and reliability. However, glass is brittle and chemically inert; TGVs have large diameters; plating time and cost are high; its poor adhesion to metals can cause delamination; and heat dissipation is poor.
Corning glass-based CPO solution
EMIB (Embedded Multi-die Interconnect Bridge): Instead of a giant, expensive interposer, a tiny, thin silicon "bridge" is embedded inside the organic substrate right under the chip edges to link them. This saves money and maintains excellent signal integrity.
3. 3D Packaging (Vertical Stacking)
3D packaging represents the ultimate evolution of CPO. Instead of placing the optical and electrical chips side-by-side, engineers stack them vertically, one directly on top of the other.
PIC as the Interposer: The electronic chip (EIC) is stacked directly on top of the optical chip (PIC) using advanced copper-to-copper hybrid bonding.
Platform Standard: TSMC's COUPE (Compact Universal Photonic Engine) 3D platform uses this approach, dropping parasitic capacitance by an incredible 85% and cutting signal latency by 95%.
ASIC chips and optoelectronic (OE) chips (or MEM-Comp modules and OE modules) are stacked on a PIC interposer, which achieves horizontal and vertical electrical interconnection through metal interconnects and TSVs. This further reduces package size, shortens chip-to-chip interconnect length, achieves high‑density integration, lowers transmission delay and noise, minimizes chip loss, and enhances thermal‑expansion reliability. TSMC's SoIC bonding technology can minimize parasitic effects at the EIC‑PIC interface, improving power and performance. However, the manufacturing process is complex, with high costs and stringent requirements for materials and fabrication precision. The TSV fabrication process (via opening, deposition of insulation/barrier/seed layers, copper filling, chemical mechanical polishing, wafer thinning, wafer bonding, etc.) is technically challenging, directly impacting TSV performance and 3D packaging reliability.
EIC as the Interposer: The PIC is stacked on top of the EIC. This allows the hot electronic chip to connect directly to the bottom substrate for easier cooling.
The PIC is flip‑chip bonded on top of the EIC, and the EIC is then interconnected with the ASIC chip through a substrate. For example, Broadcom's solution integrates a 25.6 Tbps Tomahawk 4 switching chip with four CPO optical engines in a single switch, each optical engine supporting 3.2 Tbps. This also achieves high integration density and short interconnects. Similar to using the PIC as an interposer, the complexity and cost of 3D packaging are the main challenges.
Organic Substrate Embedding: Silicon photonics are embedded directly inside an organic substrate, using built-in polymer waveguides to route light. This is highly cost-effective but prone to warping under intense heat.
Silicon photonic transceiver chips are embedded in an organic substrate and connected to a fiber-optic interface via polymer waveguides. The RDL layer is fabricated directly on the embedded silicon photonic chip and the intermediate layer, which connects to the LSI. This offers low manufacturing cost, improved chip integration, and enhanced signal transmission performance. However, the organic interposer has a high coefficient of thermal expansion (CTE) and poor dimensional stability, which limits the interconnect line width and I/O density. It also exhibits poor thermal conductivity, inadequate heat dissipation, a low elastic modulus, and is prone to warping during manufacturing.
Schematic diagram of a silicon-photonics-embedded interposer
Here is a summary of the tradeoffs across these three structural approaches:
Packaging Type
Interconnect Density
Signal Integrity
Manufacturing Cost
Thermal Management
Commercial Readiness (as of 2026)
2D Packaging
Moderate
Moderate
Low to Moderate
Fair
Mature (Broadcom Bailly, Cisco SiliconOne)
2.5D Packaging
High
High
High
Good
Scaling up (CoWoS systems)
3D Packaging
Ultra-High
Excellent
Very High
Challenging (Requires liquid cooling)
Emerging (NVIDIA Quantum-X800, TSMC COUPE)
Who Is Building CPO? The Global Ecosystem Map
CPO is not a localized effort; it has sparked a massive global collaboration across silicon design, advanced packaging, laser manufacturing, and physical cabling infrastructure.
1. International Silicon and System Giants
NVIDIA : The most aggressive driver of CPO commercialization. NVIDIA's Quantum-X800 Q3450-LD liquid-cooled CPO switch (using TSMC's 3D COUPE platform) delivers 115.2 Tbps of total bandwidth across 144 ports, completely removing the DSP to save over 3 kilowatts of power per switch rack.
Broadcom : The early pioneer. Following its Bailly 51.2T CPO switch, Broadcom introduced the Tomahawk 6 Davisson CPO ASIC, achieving single-channel speeds of 200Gbps and cutting optical power consumption by 70%.
Intel : Capitalizing on over 20 years of research, Intel is focusing on Optical Compute Interconnects (OCI) to link CPU and GPU chips directly using high-bandwidth optical paths.
Cisco & Marvell : Building custom SiliconOne CPO routers and integrated 3D Silicon Photonics engines directly inside customized XPUs.
2. Semiconductor Foundries
TSMC: Providing the foundational manufacturing engine with its COUPE platform, enabling high-volume 3D hybrid bonding of optical and electrical circuits.
Precision Alignment (FAUs): Tianfu Telecom is a global leader in high-precision FAU manufacturing and 1.6T light engines, serving as a core supplier for high-end AI CPO systems.
Laser Emitters (ELS): Lumentum and Coherent are leading developers of external laser sources. Meanwhile, companies like Yuanjie Technology have built a strong market position supplying CW-DFB laser chips.
Switch and Cooling Infrastructure: Ruijie Networks, H3C, and cooling specialists like Envic provide CPO-ready liquid cooling setups to manage high heat loads.
4. COBTEL's Role in the Ecosystem
As an OEM manufacturer of advanced optical components, COBTEL plays a crucial role in the physical infrastructure layer. CPO systems utilize incredibly high fiber counts to route laser light and signals. Our high-precision MPO fiber patch cords and custom server cabinets are specifically engineered to support the sub-micron tolerances and high density required by CPO switches and AI accelerators.
Will CPO Completely Replace Traditional Pluggable Modules?
No, CPO and pluggable optical modules will co-exist for the foreseeable future, as pluggables remain ideal for long-distance, highly flexible, and hot-swappable links, while CPO targets short-reach, ultra-dense AI clusters.
Despite the massive excitement surrounding co packaged optics, it is not a "one-size-fits-all" replacement for traditional pluggable modules. Instead, the two technologies will co-exist, each serving different roles in the network.
Pluggables: King of Long Distance and Flexibility
For long-distance data center interconnects (DCI)-such as linking two data centers across a city or state-traditional pluggable modules like our high-capacity 800G optical transceiver will remain the standard.
These links do not need ultra-dense chip integration, but they do require high flexibility. If a long-distance transmitter fails, swapping a front-panel pluggable module takes seconds and keeps the rest of the switch running.
CPO: Master of Short-Distance, Ultra-High Bandwidth
CPO's home is inside the AI cluster. For connecting GPUs to other GPUs, or linking spine switches inside a single hall where distances are short (under 100 meters), bandwidth density and power savings are the ultimate priorities.
In this space, CPO is unmatched.
Industry analysts estimate that CPO will account for roughly 1% of AI-related optical modules shipped. However, as 1.6T and 3.2T architectures scale up, CPO market penetration is projected to climb to 20%–35% between 2028 and 2030.
The Stepping Stone: Near-Packaged Optics (NPO)
Because the leap from traditional pluggables to full CPO is technically complex, the industry has embraced an intermediate step called Near-Packaged Optics (NPO).
In NPO, the optical engine is not placed on the expensive silicon substrate with the ASIC. Instead, it sits on the motherboard right next to the ASIC. This shortens the electrical path significantly compared to pluggables, but avoids the high packaging costs and thermal challenges of full CPO. It serves as a reliable stepping stone for data center operators who want better efficiency without the manufacturing risks of 3D integration.
COBTEL: The Physical "Optical Puzzle Piece" for AI Computing Power
As networks transition from traditional architectures to co packaged optics, the demand for precision, low-loss physical cabling scales up exponentially. A CPO switch may package its optical engines on-chip, but those engines still need to connect to the outside world through hundreds of optical fibers.
This is where COBTEL's 20+ years of manufacturing expertise comes in.
We provide the complete physical infrastructure supporting high-speed optical transitions:
Sub-Micron Polished Assemblies: Our MPO and high-density breakout fiber cables ensure that the fiber-to-chip interfaces suffer minimal insertion loss.
High-Speed Pluggables: We continue to manufacture robust fiber transceiver types from 10G to 800G, supporting hybrid network deployments where pluggables and CPO systems run side-by-side.
Integrated Cabling Cabinets: Our structural server racks and cable management tools are designed to organize the massive fiber bundles that CPO systems demand, ensuring optimal cooling and bend-radius safety.
When we design high-density fiber arrays and MPO breakout setups for hyperscale environments, our engineering team focuses heavily on sub-micron polishing and custom cabinet management to avoid any signal degradation. We control the entire process-from design and mold-making to testing and automated assembly-ensuring that your physical layers are fully ready for the next generation of computing.
Frequently Asked Questions
1. What is the difference between co packaged optics and pluggable optical transceivers?
Pluggable transceivers are separate, hot-swappable modules inserted into the front panel of a switch, communicating with the switch chip over long copper PCB tracks. Co packaged optics (CPO) integrates the optical engine directly with the switch chip on a single substrate, reducing the electrical signal path to just a few millimeters to save power and improve signal quality.
2. Why does CPO use silicon photonics instead of traditional laser chips?
CPO uses silicon photonics because it allows optical components to be manufactured using standard CMOS semiconductor equipment, enabling microscopic optical waveguides and modulators to be built directly onto a silicon die. This makes it possible to mass-produce and package optical engines alongside computer processors and switch ASICs in the same cleanroom environment.
3. What is Near-Packaged Optics (NPO), and how does it differ from CPO?
Near-Packaged Optics (NPO) is a transitional design where the optical engines sit on the switch motherboard immediately next to the switch chip rather than sharing the same silicon substrate. NPO offers a much shorter signal path than traditional front-panel pluggables while avoiding the extreme thermal, yield, and alignment complexities of fully co packaged optics (CPO).
4. What cabling infrastructure does a CPO switch require?
Because CPO switches pack hundreds of optical channels into a very small area, they require high-density, low-loss fiber optic assemblies, primarily using multi-fiber MPO/MTP patch cords and custom-designed high-density fiber breakout panels. Precision, dust-free connections and sub-micron polished connectors are absolutely critical to prevent signal degradation at these ultra-high speeds.
5. How does liquid cooling relate to co packaged optics systems?
Switch chips (ASICs) run incredibly hot, and in a CPO system, the temperature-sensitive optical engines are packaged directly next to them on the same substrate. Because traditional air cooling cannot safely remove this concentrated heat, CPO switches almost always rely on liquid cooling plates or direct-to-chip liquid cooling systems to keep both the ASIC and the optics within safe operating temperatures.
